It is desirable to reduce component count and current consumption of a radio section in portable telephones or the like. To address these needs, a kind of frequency synthesizer to switch between frequency channels (CH) for transmitting and receiving has been used.
Referring now to FIG. 21(a), a block schematic diagram of a conventional N frequency synthesizer is set forth and given the general reference character 2100. Conventional N frequency synthesizer 2100 is an integer frequency dividing circuit with examples of numerical values of frequency shown within parentheses.
Conventional N frequency synthesizer 2100 includes a phase comparator (PD) 1A, a charge pump (CP) 2A, a low pass filter (LPF) 3A, a voltage controlled oscillator (VCO) 4A, and a frequency dividing circuit 5A. Frequency dividing circuit 5A is able to switch between frequency dividing numbers of integers.
Phase comparator 1A receives a reference signal REF and a comparison signal SIG. Comparison signal SIG is obtained by dividing an output signal OUT of voltage controlled oscillator 4A with frequency dividing circuit 5A. Phase comparator 1A detects a phase difference between reference signal REF and comparison signal SIG and provides an output to output terminals provided as inputs to charge pump 2A. The outputs of phase comparator 1A are phase error signals which are different in polarity in accordance with the directions (lagging or leading) of phase between comparison signal SIG and reference signal REF. Furthermore, the phase error signals have a pulse width in accordance with the magnitude of phase difference between comparison signal SIG and reference signal REF.
Charge pump 2A receives the phase error signals and provides a signal CPOUT having a pulse width and polarity in accordance with phase error signals corresponding to the phase difference between comparison signal SIG and reference signal REF. Low pass filter (LPF) 3A extracts a low frequency component of signal CPOUT to provide an output received as an input to voltage controlled oscillator (VCO) 4A. VCO 4A provides an output OUT having an oscillation frequency in accordance with the output of LPF 3A. Frequency dividing circuit 5A divides output OUT by a frequency number N to provide comparison signal SIG.
Conventional N frequency synthesizer 2100 performs a feedback operation to lock the output frequency of VCO 4A so that the output of frequency divider circuit 5A (comparison signal SIG) obtained by dividing the output signal OUT of VCO 4A by a frequency dividing number N (an integer) may conform with the frequency (fref) of reference signal REF. Therefore, conventional frequency synthesizer 2100 can provide an output signal OUT of a frequency (N×fref) which is N times higher than the frequency of the reference signal REF. In this way, a channel frequency can be output having a frequency that is an integer multiple of a frequency (fref) of a reference signal REF by setting the integer N. FIG. 21(b) is a frequency diagram indicating frequencies of output signal OUT set by setting a value of N.
However, by using an integer N to set the frequency of an output signal OUT with respect to the reference signal REF, the frequency (fref) of reference signal REF is required to be identical to the difference in frequency between channels. For this reason, the frequency (fref) of reference signal REF is limited and cannot be a high frequency. Thus, the loop bandwidth becomes narrow and it may be impossible to realize high-speed locking in switching of channels or the like.
For this reason, a conventional fractional N frequency synthesizer has been proposed which uses a frequency dividing circuit which can be operated to switch among dividing operations by frequency dividing numbers of a plurality of different integers and thus performs frequency dividing with a frequency dividing number of a non-integer on average (dividing by a non-integer or dividing by a fraction). In this way, the generation of a voltage controlled oscillator output of a desired frequency is performed while allowing the frequency of a reference signal to be increased to permit high speed locking.
Referring now to FIG. 22, a block schematic diagram of a conventional N frequency synthesizer is set forth and given the general reference character 2200. Conventional N frequency synthesizer 2200 includes the basic configuration of conventional N frequency synthesizer 2100 that forms a phase locked loop (PLL). However, conventional N frequency synthesizer 2200 uses a frequency dividing circuit 5B that is able to perform frequency dividing by a frequency dividing number which can be switched to any one of frequency dividing numbers from N to N+1. Conventional N frequency synthesizer 2200 also includes a frequency dividing number control circuit 6B. Frequency dividing number control circuit 6B controls the frequency dividing number of frequency dividing circuit 5B on a time sequence basis according to a signal sequence n.
Frequency dividing number control circuit 6B receives a value (N+F/M, where N, F, M are positive integers) for the frequency dividing number of a non-integer and outputs a signal sequence n of the values of frequency dividing numbers on a time sequence basis to frequency dividing circuit 5B. Frequency dividing number control circuit 6B and frequency dividing circuit 5B provide a frequency dividing operation based on a fractional control performing non-integer frequency dividing operation from a time average value produced by switching among a plurality of integer frequency dividing operations. To do this, a type of sigma-delta moderation circuit having a noise shaping effect that is capable of removing pattern noise is used for frequency dividing number control circuit 6B to provide signal sequence n. In this way, a spurious noise pattern may not be produced in the VCO output OUT due to the averaging of the frequency dividing numbers over time.
Referring now to FIG. 23, a schematic diagram of a frequency dividing number control circuit is set forth and given the general reference number 2300. Frequency dividing number control circuit 2300 is configured as a three-stage first-order MASH, which includes sigma-delta modulators (1C, 2C, and 3C) cascaded in series, a weighting adder 4C, and an adder 5C. Each sigma-delta modulator (1C, 2C, and 3C) includes accumulators having an output provided as feedback through a delay stage D to an input. Weighting adder 4C adds the outputs of each sigma-delta modulator (1C, 2C, and 3C) either directly or through delay circuits D.
Each sigma-delta modulator (1C, 2C, and 3C) of three-stage first-degree MASH synchronously operates according to a clock (not shown). The clock has a period of the delay time of the delay circuit D. First stage sigma-delta modulator 1C accumulates input F in accumulator in accordance with the timing of the above-mentioned clock. When the accumulated value reaches M, first stage sigma-delta modulator 1C outputs an overflow signal and, at the same time, resets the accumulated value. As a result a signal of F/M is provided. Second and third stage sigma-delta modulators (2C and 3C) perform an accumulating operation according to outputs at each clock time of the first stage sigma-delta modulator 1C and second stage sigma-delta modulator 2C, respectively, an provide overflow signals and resetting in the same manner as the first stage sigma-delta modulator 1C.
Weighting adder 4C receives, with respect to the overflow signal from first stage sigma-delta modulator 1C, the overflow outputs of second and third stage sigma-delta modulators (2C and 3C) and their inverted signals after one or two clocks. Weighting adder 4C then performs a weighted addition of the overflow outputs. In this way, variations of the above F/M is randomized and the noise-shaping effect is provided. Adder 5C adds a value N to a value F/M and outputs signal sequence n on a time sequence basis.
In conventional N frequency synthesizer 2200, comparison signal SIG is locked in a steady state such that a phase difference between comparison signal SIG and reference signal REF may be near zero. In this way, VCO 4B oscillates at a frequency (N+F/M) times higher than reference signal REF and spurious pattern noise may be suppressed.
Japanese Patent Laid-Open No. 10-163860 discloses a PLL circuit using a phase comparison circuit (2) having an edge comparison function with a dead zone characteristic. The dead zone is a range in which a phase difference between a reference signal (REF) and a feedback signal (FDBK) is set as zero. This dead zone range is a given range close to zero. The PLL circuit of Japanese Patent Laid-Open No. 10-163860 also includes a frequency dividing-by-n circuit (6) (n is an integer greater than or equal to 1) and a modulator circuit (1). The modulator circuit (1) is provided on one side of either the reference signal (REF) or the feedback signal (FDBK). In this way, the occurrence of jitter in a VCO output (OUT) caused by the above-mentioned dead zone characteristic may be prevented even in a state of phase synchronization.
In a conventional fractional N frequency synthesizer, the frequency dividing circuit performs the operation of switching between a frequency dividing number N and N+1 according to the signal sequence n of dividing values on a time sequence basis. Thus, spurious pattern noise based on a time average value of the frequency dividing numbers is generated in the VCO output. However, this spurious pattern noise may be sufficiently suppressed by the frequency dividing number control having the noise shaping effect or the like as described above.
However, in a conventional fractional N frequency synthesizer, a phenomenon may exist that even the use of a frequency dividing number control as described above can leave spurious pattern noise. The frequency of this spurious component occurs at positions on higher and lower sides separated, with respect to the frequency (fvco) of the VCO output, by a frequency corresponding to a frequency difference between the frequency (fvco) and the Nth harmonic fref (fsig) of the reference signal REF. The cause of the occurrence of such a spurious pattern noise is believed to result from a portion of the VCO output sneaking into the input side of the phase comparison circuit through the package, a power supply line, a ground line, and/or other circuits on the board.
Referring now to FIG. 24, a spectral graph illustrating the frequency and power of the spurious pattern noise is set forth. FIG. 24(a) is a spectral graph showing the frequency and power of the VCO output of a frequency synthesizer of integer multiplication. FIG. 24(b) is a spectral graph showing the frequency and power of the VCO output of a fractional N frequency synthesizer.
As shown in FIG. 24(a) the frequency (fvco) of the VCO output of the frequency synthesizer of integer multiplication (for example frequency synthesizer 2100 illustrated in FIG. 21) is an integer (N) times the frequency of (fref) of the reference signal REF that can be expressed by fvco=N×fref (fsig). In a state of phase synchronization, the frequency (fvco) is an integer N times the frequency (fsig) of the comparison signal SIG, but hereinafter, the description is done in relation to the frequency (fref) of the reference signal REF. Therefore, in conventional frequency synthesizer 2100 illustrated in FIG. 21, even if the VCO output sneaks into the input side of the phase comparison circuit, spurious pattern noise of a low frequency component may not be caused by the VCO output mixing with the reference signal REF.
On the other hand, in the case of a conventional fractional N frequency synthesizer performing frequency dividing by a non-integer, the frequency (fvco) of the VCO output is a non-integer (N+F/M) times the frequency (fref) of the reference signal REF as illustrated in FIG. 24(b) (that is, fvco=(N+F/M)×fref (fsig)). Therefore, when the VCO output sneaks into the input side of the phase comparison circuit as a result of mixing with the reference signal REF, a frequency difference Δf between the VCO output and the Nth harmonic of the frequency (fref) of the reference signal REF occurs. This frequency component is present in a low frequency region, and this may be difficult to remove by filtering. That is, the signal component having the frequency difference Δf is included in the control signal of the VCO as is and becomes spurious pattern noise at a position separated from fvco by Δf at both a higher frequency and lower frequency in the frequency spectrum.
Referring now to FIG. 25, a graph of the spectrum of the VCO output in a small frequency range is set forth. The graph of FIG. 25 illustrates spurious noise occurring at F/M×fref, for example, {fraction (1/64)}×6.4 MHz=100 KHz offset in both a higher frequency and lower frequency from fvco (1280.1 MHz). This spurious noise degrades the noise characteristic of the frequency synthesizer. The spurious noise is noise of a basically different property than the above pattern noise and may not be removed by the frequency dividing number control providing a conventional noise shaping effect.
The official gazette of Japanese Patent Laid-Open No. 10-163860 discloses a PLL circuit in which the PLL circuit has a dead zone characteristic in which the phase comparison output of a phase comparison circuit becomes zero in proximity of phase difference zero even in a state of phase lock. Thus, negative feedback control may not function within the above dead zone and the occurrence of jitter in the VCO output may be prevented. However, this PLL circuit does not perform fractional control over the frequency dividing circuit, but continuously performs dividing by an integer n (n is greater than or equal to 1). Therefore, the PLL circuit of Japanese Patent Laid-Open No. 10-163860 may not remove spurious noise caused by the occurrence of the above low frequency component. From the above description, it may be apparent that the jitter described in the above-mentioned official gazette is basically different from the low frequency component of spurious noise described above.
In view of the above discussion, it would be desirable to provide a fractional N frequency synthesizer that may prevent spurious noise in the VCO output caused by the VCO output sneaking into the input side of a phase comparison circuit. It would also be desirable to provide a fractional N frequency synthesizer that may prevent spurious noise over all the range of decimal values of the non-integer frequency dividing numbers.